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path: root/mirai/boot/sequence/phases/phases.zig
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6 daysBuild interrupts: route CPU exceptions to Crimson collapse screen (full ↵Bobby1-0/+2
register dump), enable timer + keyboard IRQs with EOI in dispatch, fix asm stub newline joins and IDTR bit-size assert; PMM bitmap now sized from usable RAM only
2026-02-25Add Global Descriptor Table (GDT) and Task State Segment (TSS) implementationBobby1-0/+7
- Introduced GDT constants, including selectors, access rights, and flags. - Created GDT entry structures for kernel and user segments, along with TSS descriptors. - Implemented GDT initialization and loading functions. - Developed boot sequence phases for CPU and memory initialization. - Added boot information structure to manage memory regions and kernel details. - Implemented TSS management, including core-specific TSS setup and stack allocation. - Established state management for boot sequence phases and TSS.